In the television arts, considerable efforts have been directed toward digitizing the color video signal in the analog domain, processing the digitized samples of the analog video signal to separate the chrominance and luminance components and to demodulate the chrominance components into the respective baseband signals, and then converting the digital samples back into the respective analog signals for the application thereof to the television picture tube for reproduction. A motivation for these efforts comes from the fact that digital television can offer a number of novel features--such as still picture displays, multipicture displays, direct hookups to satellite dish amplifiers, etc. As the digital circuits become faster and less expensive, the concept of digital television becomes increasingly practical and attractive.
In a digital television receiver, the two's complement binary number system is in general use because it simplifies the circuitry required for performing arithmetic manipulations. To convert a pure binary number to its positive equivalent in two's complement, a zero is added to the next-higher-significant-bit position. When the negative of a positive two's complement binary number is required, the negative binary number is formed by complementing each bit position of the positive representation and then adding a one. The decimal numbers and the corresponding two's complement binary numbers are illustratively shown in TABLE 1. The most significant bit (MSB) of the two's complement binary numbers indicates the sign. If the MSB is a zero and a one, the two's complement binary number is positive and negative respectively.
TABLE 1 ______________________________________ DECIMAL NO. TWO'S COMP. NO. ______________________________________ -128 1000 0000 -127 1000 0001 -126 1000 0010 . . -2 1111 1110 -1 1111 1111 0 0000 0000 +1 0000 0001 +2 0000 0010 . . . +126 0111 1110 +127 0111 1111 ______________________________________
An advantage of the two's complement number system is that the binary numbers are subtracted by adding the two's complement of the subtrahend to the minuend, and ignoring the carry bit. This eliminates the need for having separate circuitry for performing subtractions. For example, the subtraction (10)-(3) can be performed, instead, as an addition (10)+(-3). Thus, ##EQU1##
In the processing of the binary signals, there are situations where unwarranted sign changes occur due to overflows. The word handling capacity of a fixed-bit binary digital processing system is limited. For example, an 8-bit digital processing system can only process whole numbers between -128 (1000 0000) and +127 (0111 1111) in the two's complement binary number system. The overflows occur when the number of bits in the resulting sum or product exceed the range of numbers which the system can handle (e.g., -128 to +127 in 8-bit two's complement system).
The signal overflows in a digital signal processing system can occur in both positive and negative directions. The positive overflows occur, for instance, when two positive, 8-bit numbers are added in the two's complement system to produce an erroneous 8-bit negative number. For example, ##EQU2##
The negative overflows can, on the other hand, occur in the two's complement system, when two negative 8-bit numbers are added to generate an erroneous 8-bit positive number. For example, ##EQU3##
The overflow correction apparatus in accordance with this invention substitutes the most positive value (e.g., 0111 1111 or +127) and the most negative value (e.g., 1000 0000 or -128) for the erroneous samples when a positive and a negative overflow has occurred respectively. The overflow correction apparatus includes a circuit for generating appropriate substitute values comprising a pair of inverters connected together in series. The most significant bit (MSB) of a potentially erroneous sample is coupled to the input of the first inverter. The output of the first inverter forms the MSB of the substitute values, and is applied to the input of the second inverter. The output of the second inverter is expanded to define the least significant bits (LSB's) of the substitute values. When an overflow error condition is detected, the erroneous value of the processed sample is replaced by the appropriate substitute value.
Pursuant to a further feature of the invention, the second of the two inverters (which serves as a buffer) is eliminated, and the LSB's of the substitute values are generated directly by fanning out the MSB of the potentially erroneous samples.